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ISL6532A
Data Sheet August 2004 FN9099.3
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
The ISL6532A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller and integrated LDO to supply VDDQ with high current during S0/S1 states and standby current during S3 state. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. A buffered version of the VDDQ/2 reference is provided as VREF. An LDO controller is also integrated for AGP core voltage regulation. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching regulator and standby LDO provide a maximum static regulation tolerance of 2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V. Switching memory core output between the PWM regulator and the standby LDO during state transitions is accomplished smoothly via the internal ACPI control circuitry. The NCH signal provides synchronized switching of a backfeed blocking switch during the transitions eliminating the need to route 5V Dual to the memory supply. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the PGOOD signal indicates VTT is within spec and operational. Each output is monitored for under and over-voltage events. The switching regulator has over current protection. Thermal shutdown is integrated.
Features
* Generates 3 Regulated Voltages - Synchronous Buck PWM Controller with Standby LDO - 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference. - Glitch-free Transitions During State Changes - LDO Regulator for 1.5V Video and Core voltage * * * * * ACPI compliant sleep state control Integrated VREF Buffer PWM Controller Drives Low Cost N-Channel MOSFETs 250kHz Constant Frequency Operation Tight Output Voltage Regulation - All Outputs: 2% Over Temperature
* 5V or 3.3V Down Conversion * Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications * Simple Single-Loop Voltage-Mode PWM Control Design * Fast PWM Converter Transient Response * Under and Over-voltage Monitoring on All Outputs * OCP on the Switching Regulator * Integrated Thermal Shutdown Protection * QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile * Pb-free available
Applications
* Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs * Graphics cards - GPU and memory supplies * ASIC power supplies * Embedded processor and I/O supplies * DSP supplies
Pinout
ISL6532A (QFN) TOP VIEW
UGATE LGATE GNDP P12V NCH 22 21 20 19 GND 29 18 17 16 15 8 VDDQ 9 VDDQ 10 VTTSNS 11 P5VSBY 12 OCSET 13 VREF_OUT 14 VREF_IN PGOOD PHASE DRIVE2 FB2 GNDA COMP FB S5# 24 S3# 23
28 GNDP 5VSBY GNDQ GNDQ VTT VTT VDDQ 1 2 3 4 5 6 7
27
26
25
Ordering Information
PART NUMBER ISL6532ACR ISL6532ACRZ (See Note) TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 28 Ld 6x6 QFN 28 Ld 6x6 QFN (Pb-free) PKG. DWG. # L28.6x6 L28.6x6
*Add "-T" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Block Diagram
P5VSBY VDDQ S3 REGULATOR + VDDQ(3) VOLTAGE REFERENCE 0.800V 0.680V (-15%) 0.920V (+15%)
S3#
S5#
5VSBY
5V POR
12VCC
2
VTTSNS VTT - REG + VTT(2) S3 SLEEP, SOFT-START, PGOOD, AND FAULT LOGIC GNDQ DISABLE S0 S0/S3 RU VREF_IN
+ + UV/OV3 UV/OV PWM ENABLE
EA2 DRIVE2 650 OUTPUT IMPEDANCE FB2 NCH
ISL6532A
{ {
+ + UV/OV2 VREF_OUT
SOFT-START + + COMP PWM PWM LOGIC
12V POR P12V UGATE
EA1
OSCILLATOR
250kHz
RL GNDA
+
UV/OV1
+ OC COMP 20A
PHASE
LGATE
PGOOD
FB
COMP
OCSET
GNDP
ISL6532A Simplified Power System Diagram
5VSBY 12V 5V
ISL6532A NCH SLP_S3 SLP_S5 SLEEP STATE LOGIC PWM CONTROLLER Q2 Q1 VDDQ +
5VSBY/3V3SBY STANDBY LDO
VDDQ LINEAR CONTROLLER
VREF VTT REGULATOR + VTT
Q3 VAGP +
Typical Application - 5V or 3.3V Input
5VSBY +3.3V +12V CBP P5VSBY 5VSBY +5V or +3.3V P12V RNCH NCH
PGOOD VDDQ VREF SLP_S3 S3# S5#
Q4 + ROCSET
SLP_S5 VREF_OUT VREF_IN +
OCSET UGATE PHASE Q1
CIN VDDQ
LOUT + Q2
2.5V
VTT + VDDQ CVTT_OUT
VTT VTT
ISL6532A
LGATE VDDQ VDDQ VDDQ GNDQ GNDQ FB COMP
CVDDQ_OUT
VTTSNS Q3 VAGP 1.5V + COUT2 FB2 GNDP GNDA DRIVE2
3
ISL6532A Typical Application - Input From 5V Dual
5VSBY +3.3V +12V CBP P5VSBY 5VSBY 5V Dual P12V
PGOOD VDDQ VREF SLP_S3 SLP_S5 S3# S5# OCSET ROCSET UGATE PHASE Q1 LOUT + LGATE VDDQ VDDQ VDDQ GNDQ GNDQ FB COMP FB2 + COUT2 GNDP GNDA Q2 CVDDQ_OUT VDDQ 2.5V + CIN NCH
VREF_OUT VREF_IN
VTT + VDDQ CVTT_OUT
VTT VTT
ISL6532A
VTTSNS Q3 VAGP 1.5V DRIVE2
4
ISL6532A
Absolute Maximum Ratings
5VSBY, P5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LEVEL 1
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (oC/W) JC (oC/W) QFN Package . . . . . . . . . . . . . . . . . . . 32 5 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Supply Voltage onP5VSBY . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER 5VSBY SUPPLY CURRENT Nominal Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC_S0 ICC_S3 ICC_S5
S3# & S5# HIGH, UGATE/LGATE Open S3# LOW, S5# HIGH, UGATE/LGATE Open S5# LOW, S3# Dont't Care, UGATE/LGATE Open
3.00 3.50 300
5.25 -
7.25 4.75 800
mA mA A
POWER-ON RESET Rising 5VSBY POR Threshold Falling 5VSBY POR Threshold Rising P12V POR Threshold Falling P12V POR Threshold OSCILLATOR AND SOFT-START PWM Frequency Ramp Amplitude Error Amp Reset Time VDDQ Soft-Start Interval REFERENCE VOLTAGE Reference Voltage System Accuracy PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate STATE LOGIC S3# Transition Level S5# Transition Level VS3 VS5 1.5 1.5 V V GBWP SR Guaranteed By Design 15 80 6 dB MHz V/s VREF -2.0 0.800 +2.0 V % fOSC VOSC tRESET tSS Mechanical Off/S5 to S0 Mechanical Off/S5 to S0 220 6.5 6.5 250 1.5 280 9.5 9.5 kHz V ms ms 4.00 3.60 10.0 8.80 4.35 3.95 10.5 9.75 V V V V
5
ISL6532A
Electrical Specifications
PARAMETER PWM CONTROLLER GATE DRIVERS UGATE and LGATE Source UGATE and LGATE Sink NCH BACKFEED CONTROL NCH Current Sink NCH Trip Level VDDQ STANDBY LDO Output Drive Current P5VSBY = 5.0V P5VSBY = 3.3V VTT REGULATOR Upper Divider Impedance Lower Divider Impedance VREF_OUT Buffer Source Current Maximum VTT Load Current RU RL IVREF_OUT IVTT_MAX Periodic load applied with 30% duty cycle and 10ms period using ISL6532AEVAL1 evaluation board (see Application Note AN1056) -3 2.5 2.5 2 3 k k mA A 650 550 mA mA INCH VNCH NCH = 0.8V 9.0 9.5 6 10.0 mA V IGATE IGATE -0.8 0.8 A A Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams and Typical Application Schematics (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
LINEAR REGULATOR DC GAIN Gain Bandwidth Product Slew Rate DRIVE2 High Output Voltage DRIVE2 Low Output Voltage DRIVE2 High Output Source Current DRIVE2 Low Output Sink Current PGOOD PGOOD Rising Threshold PGOOD Falling Threshold PROTECTION OCSET Current Source VDDQ OV Level VDDQ UV Level Linear Regulator OV Level Linear Regulator UV Level Thermal Shutdown Limit IOCSET VFB/VREF VFB/VREF VFB2/VREF VFB2/VREF TSD S0 S0 S0 S0 By Design 17 20 115 85 115 85 140 22 A % % % % C VVTTSNS/VVDDQ S0 VVTTSNS/VVDDQ S0 57.5 45.0 % % GBWP SR Guaranteed By Design 15 10.0 -.5 .85 80 6 10.2 0.16 -1.4 1.3 0.40 dB MHz V/s V V mA mA
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ISL6532A Functional Pin Description
5VSBY (Pin 2)
5VSBY is the bias supply of the ISL6532A. It is typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6532A enters a reduced power mode and draws less than 1mA (ICC_S5) from the 5VSBY supply. The supply to 5VSBY should be locally bypassed using a 0.1F capacitor. The FB pin is also monitored for under and over-voltage events.
PHASE (Pin 20)
Connect this pin to the upper MOSFET's source. This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection.
OCSET (Pin 12)
Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 20A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCSET xR OCSET I PEAK = -----------------------------------------------r DS ( ON )
P12V (Pin 25)
P12V provides the gate drive to the switching MOSFETs of the PWM power stage. The VTT regulation circuit and the Linear Driver are also powered by P12V. P12V is not required except during S0/S1/S2 operation. P12V is typically connected to the +12V rail of an ATX power supply.
5VSBY (Pin 11)
This pin provides the VDDQ output power during S3 sleep state. The regulator is capable of providing standby VDDQ power from either the 5VSBY or 3.3VSBY rail. It is recommended that the 5VSBY rail be used as the output current handling capability of the standby LDO is higher than with the 3.3VSBY rail.
An over-current trip cycles the soft-start function.
VDDQ (Pins 7, 8, 9)
The VDDQ pins should be connected externally together to the regulated VDDQ output. During S0/S1 states, the VDDQ pins serve as inputs to the VTT regulator and to the VTT Reference precision divider. During S3 state, the VDDQ pins serve as an output from the integrated standby LDO.
GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)
The GND terminals of the ISL6532A provide the return path for the VTT LDO, standby LDO and switching MOSFET gate drivers. High ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible. GNDA is the Analog ground pin, GNDQ is the return for the VTT regulator and GNDP is the return for the upper and lower gate drives.
VTT (Pins 5, 6)
The VTT pins should be connect externally together. During S0/S1 states, the VTT pins serve as the outputs of the VTT linear regulator. During S3 state, the VTT regulator is disabled.
VTTSNS (Pin 10)
VTTSNS is used as the feedback for control of the VTT linear regulator. Connect this pin to the VTT output at the physical point of desired regulation.
UGATE (Pin 26)
UGATE drives the upper (control) FET of the VDDQ synchronous buck switching regulator. UGATE is driven between GND and P12V.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of VTT and also acts as the reference voltage for the VTT linear regulator. It is recommended that a minimum capacitance of 0.1F is connected between VDDQ and VREF_OUT and also between VREF_OUT and ground for proper operation.
LGATE (Pin 27)
LGATE drives the lower (synchronous) FET of the VDDQ synchronous buck switching regulator. LGATE is driven between GND and P12V.
VREF_IN (Pin 14)
A capacitor, CSS, connected between VREF_IN and ground is required. This capacitor and the parallel combination of the Upper and Lower Divider Impedance (RU||RL), sets the time constant for the start up ramp when transitioning from S3 to S0/S1/S2. The minimum value for CSS can be found through the following equation:
C VTTOUT V DDQ C SS > -----------------------------------------------10 2A RU || R L
FB (Pin 15) and COMP (Pin 16)
The VDDQ switching regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. The positive input of the error amplifier is connected to a precision 0.8V reference and the output of the error amplifier is connected to the COMP pin. The VDDQ output voltage is set by an external resistor divider connected to FB. With a properly selected divider, VDDQ can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. Loop compensation is achieved by connecting an AC network across COMP and FB.
7
ISL6532A
The calculated capacitance, CSS, will charge the output capacitor bank on the VTT rail in a controlled manner without reaching the current limit of the VTT LDO. ACPI compliance is realized through the SLP_S3 and SLP_S5 sleep signals and through monitoring of the 12V ATX bus.
NCH (Pin 22)
NCH is an open-drain output that controls the MOSFET blocking backfeed from VDDQ to the input rail during sleep states. A 2k or larger resistor is to be tied between the 12V rail and the NCH pin. Until the voltage on the NCH pin reaches the NCH trip level, the PWM is disabled. If NCH is not actively utilized, it still must be tied to the 12V rail through a resistor. For systems using 5V dual as the input to the switching regulator, a time constant, in the form of a capacitor, can be added to the NCH pad to delay start of the PWM switcher until the 5V dual has switched from 5VSBY to 5VATX.
Initialization
The ISL6532A automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input bias supply voltages. The POR monitors the bias voltage at the 5VSBY and P12V pins. The POR function initiates soft-start operation after the bias supply voltages exceed their POR thresholds.
ACPI State Transitions
Cold Start (S4/S5 to S0 Transition) At the onset of a mechanical start, the ISL6532A receives it's bias voltage from the 5V Standby bus (5VSBY). As soon as the SLP_S3 and SLP_S5 have transitioned HIGH, the ISL6532A starts an internal counter. Following a cold start or any subsequent S4/S5 state, state transitions are ignored until the system enters S0/S1. None of the regulators will begin the soft start procedure until the 5V Standby bus has exceeded POR, the 12V bus has exceeded POR and VNCH has exceeded the trip level. Once all of these conditions are met, the PWM error amplifier will first be reset by internally shorting the COMP pin to the FB pin. This reset lasts for 2048 clock cycles, which is typically 8.2ms (one clock cycle = 1/fOSC). The digital soft start sequence will then begin. The PWM error amplifier reference input is clamped to a level proportional to the soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). The internal VTT LDO will also soft start through the reference that tracks the output of the PWM regulator. The reference for the AGP LDO controller will rise relative to the soft start reference. The soft start lasts for 2048 clock cycles, which is typically 8.2ms. This method provides a rapid and controlled output voltage rise. Figure 1 shows the soft start sequence for a typical cold start. Due to the soft start capacitance, CSS, on the VREF_IN pin, the S5 to S0 transition profile of the VTT rail will have a more rounded features at the start and end of the soft start whereas the VDDQ profile has distinct starting and ending points to the ramp up. By directly monitoring 12VATX and the SLP_S3 and SLP_S5 signals the ISL6532A can achieve PGOOD status significantly faster than other devices that depend on Latched_Backfeed_Cut for timing. Active to Sleep (S0 to S3 Transition) When SLP_S3 goes LOW with SLP_S5 still HIGH, the ISL6532A will disable the VTT linear regulator and the AGP LDO controller. The VDDQ standby regulator will be enabled
PGOOD (Pin 21)
Power Good is an open-drain logic output that changes to a logic low if any of the three regulators are out of regulation in S0/S1/S2 state. PGOOD will always be low in any state other than S0/S1/S2.
SLP_S5# (Pin 24)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 23)
This pin accepts the SLP_S3# sleep state signal.
FB2 (Pin 18)
Connect the output of the external linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for under and over-voltage events.
DRIVE2 (Pin 19)
Connect this pin to the gate terminal of an external NChannel MOSFET transistor. This pin provides the gate voltage for the linear regulator pass transistor. It also provides a means of compensating the error amplifier for applications requiring the transient response of the linear regulator to be optimized.
Functional Description
Overview
The ISL6532A provides complete control, drive, protection and ACPI compliance for a regulator powering DDR memory systems. It is primarily designed for computer applications powered from an ATX power supply. A 250kHz Synchronous Buck Regulator with a precision 0.8V reference provides the proper Core voltage to the system memory of the computer. An internal LDO regulator with the ability to both sink and source current and an externally available buffered reference that tracks the VDDQ output by 50% provides the VTT termination voltage. The ISL6532A also features an LDO regulator for 1.5V AGP Video and Core voltage.
8
ISL6532A
should be noted that the soft start profile of the VTT LDO output will vary according to the value of the capacitor on the VREF_IN pin.
12VATX 2V/DIV 5VSBY 1V/DIV VAGP 500mV/DIV VTT 500mV/DIV VDDQ 500mV/DIV S5 12VATX 2V/DIV VDDQ 500mV/DIV S3
S3 S5
VAGP 500mV/DIV
PGOOD 5V/DIV 2048 CLOCK CYCLES 12V POR 2048 CLOCK CYCLES
VTT_FLOAT VTT 500mV/DIV
SOFT START ENDS SOFT START INITIATES PGOOD COMPARATOR ENABLED
PGOOD 5V/DIV 2048 CLOCK CYCLES 12V POR PGOOD COMPARATOR ENABLED
FIGURE 1. TYPICAL COLD START
and the VDDQ switching regulator will be disabled. NCH is pulled low to disable the backfeed blocking MOSFET. PGOOD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O pins. It is important to note that the VTT rail may not bleed down to 0V. The VDDQ rail will be supported in the S3 state through the standby VDDQ LDO. When S3 transitions LOW, the Standby regulator is immediately enabled. The switching regulator is disabled synchronous to the switching waveform. The shut off time will range between 4 and 8us. The standby LDO is capable of supporting up to 650mA of load with P5VSBY tied to the 5V Standby Rail. The standby LDO may receive input from either the 3.3V Standby rail or the 5V Standby rail through the P5VSBY pin. It is recommended that the 5V Standby rail be used as the current delivery capability of the LDO is greater. Sleep to Active (S3 to S0 Transition) When SLP_S3 transitions from LOW to HIGH with SLP_S5 held HIGH and after the 12V rail exceeds POR, the ISL6532A will enable the VDDQ switching regulator, disable the VDDQ standby regulator, enable the VTT LDO and force the NCH pin to a high impedance state turning on the blocking MOSFET. The AGP LDO goes through a 2048 clock cycle soft-start. The internal short between the VTT reference and the VTT rail is released. Upon release of the short, the capacitor on VREF_IN is then charged up through the internal resistor divider network. The VTT output will follow this capacitor charge up, and acting as the S3 to S0 transition soft start for the VTT rail. The PGOOD comparator is enabled only after 2048 clock cycles, or typically 8.2ms, have passed following the S3 transition to a HIGH state. Figure 2 illustrates a typical state transition from S3 to S0. It 9
FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION
Active to Shutdown (S0 to S5 Transition) When the system transitions from active, S0, state to shutdown, S4/S5, state, the ISL6532A IC disables all regulators and forces the PGOOD pin and the NCH pin LOW.
VDDQ Over Current Protection (S0 State)
The over-current function protects the switching converter from a shorted output by using the upper MOSFET onresistance, rDS(ON), to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level (see Typical Application diagrams on pages 3 and 4). An internal 20A (typical) current sink develops a voltage across ROCSET that is referenced to the converter input voltage. When the voltage across the upper MOSFET (also referenced to the converter input voltage) exceeds the voltage across ROCSET, the overcurrent function initiates a soft-start sequence. The initiation of soft start will affect all regulators. The VTT regulator is directly affected as it receives it's reference from VDDQ. The AGP LDO will also be soft started, and as such, the AGP LDO voltage will be disabled while the VDDQ regulator is disabled. Figure 3 illustrates the protection feature responding to an over current event. At time T0, an over current condition is sensed across the upper MOSFET. As a result, the regulator is quickly shutdown and the internal soft-start function begins producing soft-start ramps. The delay interval seen
ISL6532A
by the output is equivalent to three soft-start cycles. The fourth internal soft-start cycle initiates a normal soft-start ramp of the output, at time T1. The output is brought back into regulation by time T2, as long as the over current event has cleared. Had the cause of the over current still been present after the delay interval, the over current condition would be sensed and the regulator would be shut down again for another delay interval of three soft start cycles. The resulting hiccup mode style of protection would continue to repeat indefinitely. For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
Over/Under Voltage Protection
All three regulators are protected from faults through internal Over/Under voltage detection circuitry. If the any rail falls below 85% of the targeted voltage, then an undervoltage event is tripped. An under voltage will disable all three regulators for a period of 3 soft-start cycles, after which a normal soft-start is initiated. If the output is still under 85% of target, the regulators will continue to be disabled and softstarted in a hiccup mode until the fault is cleared. This protection feature works much the same as the VDDQ PWM over current protection works. See Figure 3. If the any rail exceeds 115% of the targeted voltage, then all three outputs are immediately disabled. The ISL6532A will not re-enable the outputs until either the bias voltage is toggled in order to initiate a POR or the S5 signal is forced LOW and then back to HIGH.
VDDQ
VAGP
VTT 500mV/DIV
INTERNAL SOFT-START FUNCTION
Thermal Protection (S0/S3 State)
If the ISL6532A IC junction temperature reaches a nominal temperature of 140oC, all regulators will be disabled. The ISL6532A will not re-enable the outputs until the junction temperature drops below 110oC and either the bias voltage is toggled in order to initiate a POR or the SLP_S5 signal is forced LOW and then back to HIGH.
DELAY INTERVAL
T0 TIME
T1
T2
Shoot-Through Protection
A shoot-through condition occurs when both the upper and lower MOSFETs are turned on simultaneously, effectively shorting the input voltage to ground. To protect from a shootthrough condition, the ISL6532A incorporates specialized circuitry which insures that complementary MOSFETs are not ON simultaneously. The adaptive shoot-through protection utilized by the VDDQ regulator looks at the lower gate drive pin, LGATE, and the upper gate drive pin, UGATE, to determine whether a MOSFET is ON or OFF. If the voltage from UGATE or from LGATE to GND is less than 0.8V, then the respective MOSFET is defined as being OFF and the other MOSFET is allowed to turned ON. This method allows the VDDQ regulator to both source and sink current. Since the voltage of the MOSFET gates are being measured to determine the state of the MOSFET, the designer is encouraged to consider the repercussions of introducing external components between the gate drivers and their respective MOSFET gates before actually implementing such measures. Doing so may interfere with the shootthrough protection.
FIGURE 3. VDDQ OVER CURRENT PROTECTION AND VTT/VAGP LDO UNDER VOLTAGE PROTECTION RESPONSES
The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET x R OCSET I PEAK = ---------------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for:
( I ) I PEAK > I OUT ( MAX ) + --------- ,where I is 2
the output inductor ripple current.
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ISL6532A Application Guidelines
Layout Considerations
Layout is very important in high frequency switching converter design. With power devices switching efficiently at 250kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. As an example, consider the turn-off transition of the control MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL6532A switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 4 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the GATE pins to the MOSFET gates should be kept short and wide enough to easily handle the 1A of drive current. In order to dissipate heat generated by the internal VTT LDO, the ground pad, pin 29, should be connected to the internal ground plane through at least four vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL6532A first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as
12VATX P12V GNDP ISL6532A NCH 5VSBY P5VSBY 5VSBY GNDP UGATE PHASE LGATE COMP C2 R2 FB R4 C1 R1 C3 R3 Q2 COUT1 LOAD LOAD CBP CIN CBP VIN_DDR
Q1 LOUT
VDDQ
VDDQ(3) VTT(2) LOAD COUT2
VDDQ VTT
VIN_AGP DRIVE2 GND PAD FB2 R6 COUT3 Q3 R5 VAGP
KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
possible. Position the output inductor and output capacitors between the upper and lower MOSFETs and the load. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the PWM converter compensation components close to the FB and COMP pins. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node.
11
ISL6532A
The PWM wave is smoothed by the output filter (LO and CO).
OSC PWM COMPARATOR VOSC DRIVER VIN LO DRIVER PHASE CO VDDQ
5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier's Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary.
-
Compensation Break Frequency Equations
1 F Z1 = ----------------------------------2 x R 2 x C 2 1 F Z2 = -----------------------------------------------------2 x ( R 1 + R 3 ) x C 3 1 F P1 = ------------------------------------------------------- C 1 x C 2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C 3
+
ZFB VE/A +
ESR (PARASITIC)
-
ZIN REFERENCE
ERROR AMP
DETAILED COMPENSATION COMPONENTS C1 C2 R2 ZFB ZIN C3 R1 R3 VDDQ
COMP
+
FB R4
ISL6532A
REFERENCE
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
R 1 V DDQ = 0.8 x 1 + ------ R 4 FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC .
100 80 60 GAIN (dB) 40 20 0 -20 -40 MODULATOR GAIN 20LOG (R2/R1)
FZ1 FZ2
FP1
FP2 OPEN LOOP ERROR AMP GAIN
Modulator Break Frequency Equations
1 F LC = -----------------------------------------2 x L O x C O 1 F ESR = ------------------------------------------2 x ESR x C O
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN FESR 10K 100K 1M 10M
The compensation network consists of the error amplifier (internal to the ISL6532A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero. 12
FLC -60 10 100 1K
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This LDO, which uses a MOSFET as the linear pass element, requires feedback compensation to insure stability of the system. The LDO requires compensation because of the output impedance of the error amplifier.
ISL6532A
ISL6532A 0.8V REFERENCE + 650 OUTPUT IMPEDANCE FB2 R8 R9 ESR RLOAD + DRIVE2
Component Selection Guidelines
VDDQ
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. DDR memory systems are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
C25
R10
VAGP
R 8 V AGP = 0.8 x 1 + ------ R 9
COUT
FIGURE 7. COMPENSATION AND OUTPUT VOLTAGE SELECTION OF THE LINEAR
To properly compensate the LDO system, a 100k 1% resistor and a 680pF X5R ceramic capacitor, represented as R10 and C25 in Figure 7, are used. This compensation will insure a stable system with any MOSFET given the following conditions:
= C OUT ESR > 10s R FB = R 8 = 249
Maximum bandwidth will be realized at full load while minimum bandwidth will be realized at no load. Bandwidth at no load will be maximized as becomes closer to 10s.
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be programmed to any level between VIN and the internal reference, 0.8V. An external resistor divider is used to scale the output voltage relative to the reference voltage and feed it back to the inverting input of the error amplifier, see Figure 5. However, since the value of R1 affects the values of the rest of the compensation components, it is advisable to keep its value less than 5k. Depending on the value chosen for R1, R4 can be calculated based on the following equation:
R1 x 0.8V R4 = ----------------------------------V DDQ - 0.8V
Output Capacitor Selection - LDO Regulators
The output capacitors used in LDO regulators are used to provide dynamic load current. The amount of capacitance and type of capacitor should be chosen with this criteria in mind.
If the output voltage desired is 0.8V, simply route VDDQ back to the FB pin through R1, but do not populate R4. The output voltage for the internal VTT linear regulator is set internal to the ISL6532A to track the VDDQ voltage by 50%. There is no need for external programming resistors. As with the VDDQ PWM regulator, the AGP linear regulator output voltage is set by means of an external resistor divider as shown in Figure 7. For stability concerns described earlier, the recommended value of the feedback resistor, R8, is 249. The voltage programming resistor, R9 can be calculated based on the following equation:
R 8 x 0.8V R 9 = ---------------------------------V AGP - 0.8V
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR
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ISL6532A
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6532A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT
For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6532A requires 2 N-Channel power MOSFETs for switching power and a third MOSFET to block backfeed from VDDQ to the Input in S3 Mode. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the equations below). These equations assume linear voltage-current transitions and do not adequately model power loss due the reverserecovery of the upper and lower MOSFET's body diode. The gate-charge losses are dissipated in part by the ISL6532A and do not significantly heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Approximate Losses while Sourcing current
2 1 P UPPER = Io x r DS ( ON ) x D + -- Io x V IN x t SW x f s 2
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection - PWM Buck Converter
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSFET and the source of lower MOSFET. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current required by the regulator may be closely approximated through the following equation:
I RMS = V IN - V OUT V OUT 2 V OUT 2 1 ------------- x I OUT + ----- x ---------------------------- x ------------- V IN V IN 12 L x f s MAX
PLOWER = Io2 x rDS(ON) x (1 - D)
Approximate Losses while Sinking current
PUPPER = Io2 x rDS(ON) x D
2 1 P LOWER = Io x r DS ( ON ) x ( 1 - D ) + -- Io x V IN x t SW x f s 2
Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and fs is the switching frequency.
MAX
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ISL6532A
MOSFET Selection - AGP LDO
The main criteria for selection of the linear regulator pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is:
P LINEAR I O x ( V IN - V OUT )
ISL6532A Application Circuit
Figure 8 shows an application circuit utilizing the ISL6532A. Detailed information on the circuit, including a complete Billof-Materials and circuit board description, can be found in Application Note AN1056.
where IO is the maximum output current and VOUT is the nominal output voltage of the linear regulator.
5VSBY +3.3V R2 10.0k PGOOD VDDQ VREF C26 0.1F C17,18 1F VCC12 R1 4.99k C16 1F 5VSBY P5VSBY P12V
VCC5
Q5
PGOOD SLP_S5 SLP_S3 S5# S3# VREF_OUT C27 0.1F VREF_IN
NCH C22 1000pF
L1 2.1H
OCSET R7 UGATE PHASE ISL6532A 8.87k Q1,3
C4,5 1F
+
C1-3 2200F VDDQ 2.5V 15AMAX
VDDQ VTT 1.25V C20+ 220F VDDQ + C21 220F
C19 0.47F
L2 2.1H LGATE VDDQ VDDQ VDDQ GNDQ GNDQ FB R4 1.74k Q2,4
+
VTT VTT VTTSNS
C6-8 1800F
C9-12 22F
Q4
DRIVE2 R10 100k
1.5V + C24 1F C23 220F
C25 680pF FB2 R8 249 R9 287
GNDA
GNDP
GNDP
VAGP
COMP C15 1000pF C14 6.8nF R3 19.1k
C13 56nF
R5 22.6
R6 825
FIGURE 8. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532A
15
ISL6532A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 3.95 3.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 6.00 BSC 5.75 BSC 4.10 6.00 BSC 5.75 BSC 4.10 0.65 BSC 0.60 28 7 7 0.60 12 0.75 0.15 4.25 4.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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